Designing Your Own PCIe JPEG Encoder on FPGA

introduction video clip : https://www.youtube.com/watch?v=30IyLIe_UO0

Target audience of this 110-pages book(55 in dual page mode) is for who wants to efficiently:

• Learn practical FPGA design: A complete design from design architecture, testbench for simulation, coding, then Synthesis & Implementation to Timing Closure
• Write a Linux C++ program to test this PCIe FPGA JPEG encoder (with DMA and device driver)

At the FPGA side, you will use and design

• JPEG Encoder: this Open-source hardware IP will compress the raw image pixels into compressed JPEG image (think about this: Originally this was done by a software program to do this)
• PCIe Endpoint (x1/x4/x8): the interface for data transmission between FPGA and X86 Host
• DMA Engine: the Xilinx DMA IP for PCIe and User Logic (JPEG Encoder)
• DDRx Memory Controller: FPGA side memory for DMA/User Data
• Control Registers: for configuration and handshake signals with Linux C/C++ program
• AXI4 Memory Mapped (MM) and Stream IP: Xilinx IPs to convert data format and bridging all IPs and PCIe, Xilinx changed to use AXI4 interface for all IPs and Tools
• Custom AXI4-MM or AXI4-Stream modules Bridge: These custom modules are designed to link all of above, for example, the Open-source JPEG Encoder uses OPB Bus interface.

At the Linux X86 Host side, you will build a Linux C++ program which implements key functions

• Initialization: Initialization Linux C++ program and FPGA PCIe Encoder
• Raw image loader: load image BMP file(s) from Linux Host disk and extract raw image pixels by Linux File I/O, Memory management and other system calls. Then write the raw images pixels to FPGA DDRx Memory
• H/W JPEG Encoder Configuration: Configure the FPGA JPEG Encoder by software APIs (Linux standard Memory Writes and Reads to memory mapping registers of this the FPGA JPEG Encoder, but the writes/reads value and sequence must match the definition in FPGA modules. Let's discus this more later)
• Some important information must be set by C++ software to FPGA JPEG Encoder ,like the size of Images, chrominance and Luminance coeffficient tables, etc.
• FPGA Getting Raw image: Raw image transferred to FPGA PCIe JPEG encoder by DMA (with help of device driver)
• Polling "JPEG done" of FPGA PCIe JPEG encoder

once the compression is done, compressed JPEG bytes will be transferred to FPGA DDRx Memory by JPEG Encoder, then C++ program could read JPEG file to Host memory through DMA from FPGA PCIe DDRx Memory.

Table of Contents

CHAPTER 1 PREPARATION

1.1 Design Scope and What You Will Learn and Get

1.2 Facility, FPGA/Software IP and Prerequisite

1.3 Vivado Installation & Licensing

Chapter Summary/Key Takeaways

CHAPTER 2 FPGA DESIGN ARCHITECTURE

2.1 FPGA JPEG Encoder Design Top Schematic

2.2 JPEG Encoder Subsystem

2.3 Running Behavioral Simulation of JPEG Encoder IP

2.4 Understanding Testbench & Debugging JPEG File Format Error

Chapter Summary/Key Takeaways

CHAPTER 3 PCIE DMA JPEG ENCODER AND CUSTOM MODULES INTEGRATION

3.1 Custom AXI4 Interface JPEG Encoder and Testbench

3.2 Behavioral Simulation of AXI4 JPEG Encoder Subsystem

3.3 Custom RTL Module -Finite State Machine for JPEG DMA

3.4 Integrating PCIe JPEG Encoder by IP Integrator

3.5 Implementing PCIe JPEG Encoder and FPGA Configuration

Chapter Summary/Key Takeaways

CHAP 4 LINUX C/C++ PROGRAM FOR FPGA JPEG ENCODER

4.1 Test Program Subroutines and St

Dettagli